Comparative Analysis of Traditional Adder and Pipelined RCA

Abstract

Addition is the basic arithmetic operation in any processing system. A fast and accurate operation of digital system is greatly influenced in performance of resident adders. Hence improving the performance of adder would greatly enhance the execution of circuit operation. In Conventional adders results in high power dissipation and increased complexity when number of bits are increased. Pipelining is an emerging technique used to obtain high throughput over conventional design. The whole task can be divided into number of subtasks to speed up the operation. In this paper traditional adder is compared with pipeline based parallel RCA and it has been proven that the efficiency of pipelined adder is much higher. The results are simulated using Xilinx 12.1 and various parameters are compared and tabulated.